1. Field of the Invention
The invention generally relates to DMOS-transistors and the fabrication thereof, wherein an improvement of the electric strength of the source terminal with respect to the substrate is achieved.
2. Description of Related Art
DMOS-transistors have advantages in the circuit application compared to the standard “transistor pair” of n-type high-voltage and p-type high-voltage transistors:                no threshold voltage difference as may typically be encountered in n-type high-voltage and p-type high-voltage transistors,        identical on-resistance Ron,        less area consumption in particular compared to p-type high-voltage transistors.        
For “smart power” applications it is important that respective technical solutions can be implemented into standard CMOS technology. A DMOS-transistor of this type is for instance described in DE-A 100 63 135.
In particular in applications as a switch at the side connected to the high potential (high side switch) the source-substrate path is stressed with high voltages, wherein the electric strength is limited by the punch-through effect that will then be effective. Depending on the semiconductor material used and depending on the type of doping used a current flow may be caused at this location even at low source-substrate voltages. This current flow significantly restricts the possible applications. Also, the doping used may not be arbitrarily varied. Lightly doped n-wells among others have the advantage to ensure a high electric strength at the drain, wherein, however, the electric strength for the source-substrate path is very low. A more heavily doped n-well guarantees a higher electric strength of the source-substrate path, while however reducing the dielectric break-through strength at the drain. This can be demonstrated by simulation and experiment.
These problems have generated a plurality of solutions. In this respect, DE-A 198 40 402 describes an additional “punch-through” barrier by a boron implantation into the p-well immediately below the n+ source regions. In effect, this compares to a selective doping enhancement of the p-well (p-type body).
According to EP-A 735 591 and U.S. Pat. No. 6,069,034 the punch-through effect is to suppressed by a buried n-doped layer below the n-well. This solution, however, depends on the presence of an epitaxial layer.
According to EP-A 1 220 323 in particular avalanche effects should be reduced by incorporating an additional p-well (buried p-type body), thereby increasing a safe operating area (SOA). As a side effect also the punch-through effect is to be suppressed or is to be shifted towards significantly higher voltages.
With each of these solutions it is a disadvantage that additional process steps have to be implemented in the CMOS process flow. This is accompanied by higher costs, while also increasing the risk of influencing the previous characteristics of process components.